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- Path: watnews.watson.ibm.com!kgold
- From: kgold@watson.ibm.com (K Goldman)
- Newsgroups: comp.sys.m68k
- Subject: Re: [?] Wait state generator - 68k
- Date: 26 Mar 1996 18:16:57 GMT
- Organization: IBM T.J. Watson Research Center
- Distribution: ibm
- Message-ID: <4j9cap$cha@watnews1.watson.ibm.com>
- References: <4j5hc2$roc@pulp.ucs.ualberta.ca> <4j7j56$ffc@pulp.ucs.ualberta.ca> <ludisDovGqI.412@netcom.com>
- NNTP-Posting-Host: beta.watson.ibm.com
-
- ludis@netcom.com (Ludis Langens) writes:
- |> jdv@ee.ualberta.ca (John Voth) writes:
- |>
- |> >Another question, if the mc68k continuously monitors the DTACK line
- |> >- waiting for it to be asserted then does the mc68k wait until it is
- |> >de-asserted before ending the bus cycle? Or does the mc68k end the bus
- |> >cycle immediately after receiving the DTACK signal?
- |>
- |> The 68k polls the DTACK line once per clock cycle. Upon finding it
- |> asserted, it will allow the bus cycle to continue to its end. This
- |> takes about another full clock cycle or so before everything is done.
- |> If you assert DTACK at the correct part of the clock cycle, you can
- |> actually deassert it before the bus cycle is done.
- |>
-
- Does Ludis mean that DSACK can actually be deasserted before AS and DS
- negate. This is PROBABLY true. DSACK is sampled at the end of S2.
- If it is asserted at that time, the 68k probably negates AS and DS at
- the end of S4 and ends the cycle. It probably does not care what
- DSACK is at the end of S4.
-
- However, the data book says to keep DSACK asserted until AS and DS
- negate.
-
- --
- Ken Goldman kgold@watson.ibm.com 914-784-7396
-